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The art of timing closureadvanced AS...

Golshan, Khosrow.

The art of timing closureadvanced ASIC design implementation /

Record Type:	Electronic resources : Monograph/item
Title/Author:	The art of timing closureby Khosrow Golshan.
Reminder of title:	advanced ASIC design implementation /
Author:	Golshan, Khosrow.
Published:	Cham :Springer International Publishing :2020.
Description:	xix, 204 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Application-specific integrated circuits.
Online resource:	https://doi.org/10.1007/978-3-030-49636-4
ISBN:	9783030496364$q(electronic bk.)

The art of timing closureadvanced ASIC design implementation /
Golshan, Khosrow.

The art of timing closureadvanced ASIC design implementation /[electronic resource] :by Khosrow Golshan. - Cham :Springer International Publishing :2020. - xix, 204 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. Design Implementation Data Structures and Settings -- Chapter 3. Design Constraints Development -- Chapter 4. Multiple Modes and Multiple Corners Development -- Chapter 5. Concurrent Floor Planning and Placement -- Chapter 6. Placement and Timing Analysis -- Chapter 7. Clock Tree Synthesis and Timing Analysis -- Chapter 8. Detail Route and Timing, Power Analysis -- Chapter 9. Final Route and Timing Closure in all Modes and Corners -- Chapter 10. Functional and Physical Verification.

ISBN: 9783030496364$q(electronic bk.)

Standard No.: 10.1007/978-3-030-49636-4doiSubjects--Topical Terms:

339139
Application-specific integrated circuits.

LC Class. No.: TK7874.6 / .G65 2020

Dewey Class. No.: 621.3815

The art of timing closureadvanced ASIC design implementation /
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100 1 $a Golshan, Khosrow. $3 260808
245 1 4 $a The art of timing closure $h [electronic resource] : $b advanced ASIC design implementation / $c by Khosrow Golshan.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2020.
300 $a xix, 204 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Introduction -- Chapter 2. Design Implementation Data Structures and Settings -- Chapter 3. Design Constraints Development -- Chapter 4. Multiple Modes and Multiple Corners Development -- Chapter 5. Concurrent Floor Planning and Placement -- Chapter 6. Placement and Timing Analysis -- Chapter 7. Clock Tree Synthesis and Timing Analysis -- Chapter 8. Detail Route and Timing, Power Analysis -- Chapter 9. Final Route and Timing Closure in all Modes and Corners -- Chapter 10. Functional and Physical Verification.
650 0 $a Application-specific integrated circuits. $3 339139
650 1 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
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856 4 0 $u https://doi.org/10.1007/978-3-030-49636-4
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