國立高雄大學圖資館 |

Language: English

Back

Formal verification of floating-point hardware designa mathematical approach /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Formal verification of floating-point hardware designby David M. Russinoff.
Reminder of title:	a mathematical approach /
Author:	Russinoff, David M.
Published:	Cham :Springer International Publishing :2022.
Description:	xxviii, 436 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Formal methods (Computer science)
Online resource:	https://doi.org/10.1007/978-3-030-87181-9
ISBN:	9783030871819$q(electronic bk.)

Formal verification of floating-point hardware designa mathematical approach /
Russinoff, David M.

Formal verification of floating-point hardware designa mathematical approach /[electronic resource] :by David M. Russinoff. - Second edition. - Cham :Springer International Publishing :2022. - xxviii, 436 p. :ill., digital ;24 cm.

Part I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor.

This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I-III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.

ISBN: 9783030871819$q(electronic bk.)

Standard No.: 10.1007/978-3-030-87181-9doiSubjects--Topical Terms:

277520
Formal methods (Computer science)

LC Class. No.: QA76.9.F67 / R87 2022

Dewey Class. No.: 004.0151

Formal verification of floating-point hardware designa mathematical approach /
LDR:03609nmm a2200337 a 4500 001 622345
003 DE-He213
005 20220303140533.0
006 m d
007 cr nn 008maaau
008 221209s2022 sz s 0 eng d
020 $a 9783030871819$q(electronic bk.)
020 $a 9783030871802$q(paper)
024 7 $a 10.1007/978-3-030-87181-9 $2 doi
035 $a 978-3-030-87181-9
040 $a GP $c GP
041 0 $a eng
050 4 $a QA76.9.F67 $b R87 2022
072 7 $a UK $2 bicssc
072 7 $a COM036000 $2 bisacsh
072 7 $a UK $2 thema
082 0 4 $a 004.0151 $2 23
090 $a QA76.9.F67 $b R969 2022
100 1 $a Russinoff, David M. $3 834379
245 1 0 $a Formal verification of floating-point hardware design $h [electronic resource] : $b a mathematical approach / $c by David M. Russinoff.
250 $a Second edition.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2022.
300 $a xxviii, 436 p. : $b ill., digital ; $c 24 cm.
505 0 $a Part I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor.
520 $a This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I-III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.
650 0 $a Formal methods (Computer science) $3 277520
650 0 $a Floating-point arithmetic. $3 229083
650 1 4 $a Arithmetic and Logic Structures. $3 276274
650 2 4 $a Hardware Performance and Reliability. $3 913149
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Electronics Design and Verification. $3 919565
650 2 4 $a Computer Hardware. $3 275482
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-030-87181-9
950 $a Computer Science (SpringerNature-11645)