國立高雄大學圖資館 |

登入

回首頁

The read-out controller ASIC for the ATLAS experiment at LHC

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	The read-out controller ASIC for the ATLAS experiment at LHCby Stefan Popa.
作者:	Popa, Stefan.
出版者:	Cham :Springer International Publishing :2022.
面頁冊數:	xviii, 198 p. :ill., digital ;24 cm.
附註:	"Doctoral thesis accepted by Transilvania University of Brasov, Romania."
Contained By:	Springer Nature eBook
標題:	Particle accelerationMeasurement.
電子資源:	https://doi.org/10.1007/978-3-031-18074-3
ISBN:	9783031180743$q(electronic bk.)

The read-out controller ASIC for the ATLAS experiment at LHC
Popa, Stefan.

The read-out controller ASIC for the ATLAS experiment at LHC[electronic resource] /by Stefan Popa. - Cham :Springer International Publishing :2022. - xviii, 198 p. :ill., digital ;24 cm. - Springer theses,2190-5061. - Springer theses..

"Doctoral thesis accepted by Transilvania University of Brasov, Romania."

Introduction -- The Read-Out Controller -- ROC Testing -- Immunity to Radiation-Induced Faults -- An application -- Conclusions -- Appendices.

This thesis presents the complete chain from specifications to real-life deployment of the Read Out Controller (ROC) ASIC for the ATLAS Experiment at LHC, including the design of the FPGA-based setup used for prototype validation and mass testing of the approximately 6000 chips. Long-lasting experiments like the ATLAS at the LHC undergo regular upgrades to improve their performance over time. One of such upgrades of the ATLAS was the replacement of a fraction of muon detectors in the forward rapidities to provide much-improved reconstruction precision and discrimination from background protons. This new instrumentation (New Small Wheel) is equipped with custom-designed, radiation-hard, on-detector electronics with the Read Out Controller chip being a mission-critical element. The chip acts as a clock and control signals distributor and a concentrator, buffer, filter and real-time processor of detector data packets. The described and deployed FPGA-based test setup emulates the asynchronous chip context and employs optimizations and automatic clock and data synchronization. The chip's tolerance to nuclear radiation was evaluated by recording its operation while controlled ultrafast neutron beams were incident to its silicon die. Predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included.

ISBN: 9783031180743$q(electronic bk.)

Standard No.: 10.1007/978-3-031-18074-3doiSubjects--Topical Terms:

940513
Particle acceleration
--Measurement.

LC Class. No.: QC787.P3 / P67 2022

Dewey Class. No.: 539.73

The read-out controller ASIC for the ATLAS experiment at LHC
LDR:02711nmm a2200349 a 4500 001 634219
003 DE-He213
005 20221217205853.0
006 m d
007 cr nn 008maaau
008 230511s2022 sz s 0 eng d
020 $a 9783031180743$q(electronic bk.)
020 $a 9783031180736$q(paper)
024 7 $a 10.1007/978-3-031-18074-3 $2 doi
035 $a 978-3-031-18074-3
040 $a GP $c GP
041 0 $a eng
050 4 $a QC787.P3 $b P67 2022
072 7 $a PDDM $2 bicssc
072 7 $a TEC022000 $2 bisacsh
072 7 $a PDD $2 thema
082 0 4 $a 539.73 $2 23
090 $a QC787.P3 $b P825 2022
100 1 $a Popa, Stefan. $3 940512
245 1 4 $a The read-out controller ASIC for the ATLAS experiment at LHC $h [electronic resource] / $c by Stefan Popa.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2022.
300 $a xviii, 198 p. : $b ill., digital ; $c 24 cm.
490 1 $a Springer theses, $x 2190-5061
500 $a "Doctoral thesis accepted by Transilvania University of Brasov, Romania."
505 0 $a Introduction -- The Read-Out Controller -- ROC Testing -- Immunity to Radiation-Induced Faults -- An application -- Conclusions -- Appendices.
520 $a This thesis presents the complete chain from specifications to real-life deployment of the Read Out Controller (ROC) ASIC for the ATLAS Experiment at LHC, including the design of the FPGA-based setup used for prototype validation and mass testing of the approximately 6000 chips. Long-lasting experiments like the ATLAS at the LHC undergo regular upgrades to improve their performance over time. One of such upgrades of the ATLAS was the replacement of a fraction of muon detectors in the forward rapidities to provide much-improved reconstruction precision and discrimination from background protons. This new instrumentation (New Small Wheel) is equipped with custom-designed, radiation-hard, on-detector electronics with the Read Out Controller chip being a mission-critical element. The chip acts as a clock and control signals distributor and a concentrator, buffer, filter and real-time processor of detector data packets. The described and deployed FPGA-based test setup emulates the asynchronous chip context and employs optimizations and automatic clock and data synchronization. The chip's tolerance to nuclear radiation was evaluated by recording its operation while controlled ultrafast neutron beams were incident to its silicon die. Predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included.
650 0 $a Particle acceleration $x Measurement. $3 940513
650 0 $a Detectors. $3 197808
650 0 $a Large Hadron Collider (France and Switzerland) $x Experiments. $3 940514
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer Nature eBook
830 0 $a Springer theses. $3 557607
856 4 0 $u https://doi.org/10.1007/978-3-031-18074-3
950 $a Physics and Astronomy (SpringerNature-11651)