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The read-out controller ASIC for the ATLAS experiment at LHC

Record Type:	Electronic resources : Monograph/item
Title/Author:	The read-out controller ASIC for the ATLAS experiment at LHCby Stefan Popa.
Author:	Popa, Stefan.
Published:	Cham :Springer International Publishing :2022.
Description:	xviii, 198 p. :ill., digital ;24 cm.
Notes:	"Doctoral thesis accepted by Transilvania University of Brasov, Romania."
Contained By:	Springer Nature eBook
Subject:	Particle accelerationMeasurement.
Online resource:	https://doi.org/10.1007/978-3-031-18074-3
ISBN:	9783031180743$q(electronic bk.)

The read-out controller ASIC for the ATLAS experiment at LHC
Popa, Stefan.

The read-out controller ASIC for the ATLAS experiment at LHC[electronic resource] /by Stefan Popa. - Cham :Springer International Publishing :2022. - xviii, 198 p. :ill., digital ;24 cm. - Springer theses,2190-5061. - Springer theses..

"Doctoral thesis accepted by Transilvania University of Brasov, Romania."

Introduction -- The Read-Out Controller -- ROC Testing -- Immunity to Radiation-Induced Faults -- An application -- Conclusions -- Appendices.

This thesis presents the complete chain from specifications to real-life deployment of the Read Out Controller (ROC) ASIC for the ATLAS Experiment at LHC, including the design of the FPGA-based setup used for prototype validation and mass testing of the approximately 6000 chips. Long-lasting experiments like the ATLAS at the LHC undergo regular upgrades to improve their performance over time. One of such upgrades of the ATLAS was the replacement of a fraction of muon detectors in the forward rapidities to provide much-improved reconstruction precision and discrimination from background protons. This new instrumentation (New Small Wheel) is equipped with custom-designed, radiation-hard, on-detector electronics with the Read Out Controller chip being a mission-critical element. The chip acts as a clock and control signals distributor and a concentrator, buffer, filter and real-time processor of detector data packets. The described and deployed FPGA-based test setup emulates the asynchronous chip context and employs optimizations and automatic clock and data synchronization. The chip's tolerance to nuclear radiation was evaluated by recording its operation while controlled ultrafast neutron beams were incident to its silicon die. Predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included.

ISBN: 9783031180743$q(electronic bk.)

Standard No.: 10.1007/978-3-031-18074-3doiSubjects--Topical Terms:

940513
Particle acceleration
--Measurement.

LC Class. No.: QC787.P3 / P67 2022

Dewey Class. No.: 539.73

The read-out controller ASIC for the ATLAS experiment at LHC
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520 $a This thesis presents the complete chain from specifications to real-life deployment of the Read Out Controller (ROC) ASIC for the ATLAS Experiment at LHC, including the design of the FPGA-based setup used for prototype validation and mass testing of the approximately 6000 chips. Long-lasting experiments like the ATLAS at the LHC undergo regular upgrades to improve their performance over time. One of such upgrades of the ATLAS was the replacement of a fraction of muon detectors in the forward rapidities to provide much-improved reconstruction precision and discrimination from background protons. This new instrumentation (New Small Wheel) is equipped with custom-designed, radiation-hard, on-detector electronics with the Read Out Controller chip being a mission-critical element. The chip acts as a clock and control signals distributor and a concentrator, buffer, filter and real-time processor of detector data packets. The described and deployed FPGA-based test setup emulates the asynchronous chip context and employs optimizations and automatic clock and data synchronization. The chip's tolerance to nuclear radiation was evaluated by recording its operation while controlled ultrafast neutron beams were incident to its silicon die. Predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included.
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