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Lifetime reliability-aware design of integrated circuits

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Lifetime reliability-aware design of integrated circuitsby Mohsen Raji, Behnam Ghavami.
作者:	Raji, Mohsen.
其他作者:	Ghavami, Behnam.
出版者:	Cham :Springer International Publishing :2023.
面頁冊數:	xiii, 107 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Integrated circuitsDesign.
電子資源:	https://doi.org/10.1007/978-3-031-15345-7
ISBN:	9783031153457$q(electronic bk.)

Lifetime reliability-aware design of integrated circuits
Raji, Mohsen.

Lifetime reliability-aware design of integrated circuits[electronic resource] /by Mohsen Raji, Behnam Ghavami. - Cham :Springer International Publishing :2023. - xiii, 107 p. :ill., digital ;24 cm.

1. Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops -- 2 Restructuring-based Lifetime Reliability Improvement of Nano-scale Master-Slave Flip-Flops -- 3 Lifetime Reliability Improvement of Pulsed Flip-Flops -- 4 Gate Sizing-based Lifetime Reliability Improvement of Integrated Circuits -- 5 Joint Timing Yield and Lifetime Reliability Optimization of Integrated Circuits -- 6 Lifetime Reliability Optimization Algorithms of Integrated Circuits using Dual Threshold Voltage Assignment.

This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits. Provides an easy-to-follow procedure for analyzing lifetime reliability of nano-scale digital circuits; Describes state-of-the art aging- and process variation-aware CAD algorithms; Includes reliability improvement techniques for common clocked storage element.

ISBN: 9783031153457$q(electronic bk.)

Standard No.: 10.1007/978-3-031-15345-7doiSubjects--Topical Terms:

218965
Integrated circuits
--Design.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Lifetime reliability-aware design of integrated circuits
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505 0 $a 1. Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops -- 2 Restructuring-based Lifetime Reliability Improvement of Nano-scale Master-Slave Flip-Flops -- 3 Lifetime Reliability Improvement of Pulsed Flip-Flops -- 4 Gate Sizing-based Lifetime Reliability Improvement of Integrated Circuits -- 5 Joint Timing Yield and Lifetime Reliability Optimization of Integrated Circuits -- 6 Lifetime Reliability Optimization Algorithms of Integrated Circuits using Dual Threshold Voltage Assignment.
520 $a This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits. Provides an easy-to-follow procedure for analyzing lifetime reliability of nano-scale digital circuits; Describes state-of-the art aging- and process variation-aware CAD algorithms; Includes reliability improvement techniques for common clocked storage element.
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