國立高雄大學圖資館 |

On-chip training NPUalgorithm, architecture and SoC design /

Record Type:	Electronic resources : Monograph/item
Title/Author:	On-chip training NPUby Donghyeon Han, Hoi-Jun Yoo.
Reminder of title:	algorithm, architecture and SoC design /
Author:	Han, Donghyeon.
other author:	Yoo, Hoi-Jun.
Published:	Cham :Springer Nature Switzerland :2023.
Description:	xxiii, 237 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Systems on a chipDesign and construction.
Online resource:	https://doi.org/10.1007/978-3-031-34237-0
ISBN:	9783031342370$q(electronic bk.)

On-chip training NPUalgorithm, architecture and SoC design /
Han, Donghyeon.

On-chip training NPUalgorithm, architecture and SoC design /[electronic resource] :by Donghyeon Han, Hoi-Jun Yoo. - Cham :Springer Nature Switzerland :2023. - xxiii, 237 p. :ill. (some col.), digital ;24 cm.

Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.

ISBN: 9783031342370$q(electronic bk.)

Standard No.: 10.1007/978-3-031-34237-0doiSubjects--Topical Terms:

242476
Systems on a chip
--Design and construction.

LC Class. No.: TK7895.E42 / H36 2023

Dewey Class. No.: 621.3815

On-chip training NPUalgorithm, architecture and SoC design /
LDR:02558nmm a2200325 a 4500 001 648642
003 DE-He213
005 20230727223805.0
006 m d
007 cr nn 008maaau
008 240116s2023 sz s 0 eng d
020 $a 9783031342370$q(electronic bk.)
020 $a 9783031342363$q(paper)
024 7 $a 10.1007/978-3-031-34237-0 $2 doi
035 $a 978-3-031-34237-0
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.E42 $b H36 2023
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7895.E42 $b H233 2023
100 1 $a Han, Donghyeon. $3 958437
245 1 0 $a On-chip training NPU $h [electronic resource] : $b algorithm, architecture and SoC design / $c by Donghyeon Han, Hoi-Jun Yoo.
260 $a Cham : $b Springer Nature Switzerland : $b Imprint: Springer, $c 2023.
300 $a xxiii, 237 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.
520 $a Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.
650 0 $a Systems on a chip $x Design and construction. $3 242476
650 0 $a Integrated circuits. $3 190434
650 0 $a Neural networks (Computer science) $3 181982
650 1 4 $a Electronic Circuits and Systems. $3 913394
650 2 4 $a Embedded Systems. $3 919564
650 2 4 $a Processor Architectures. $3 274498
700 1 $a Yoo, Hoi-Jun. $3 310630
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-031-34237-0
950 $a Engineering (SpringerNature-11647)