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VLSI Design for Reliable and Stochastic Computing /

Record Type:	Electronic resources : Monograph/item
Title/Author:	VLSI Design for Reliable and Stochastic Computing /Yibo Liu.
Author:	Liu, Yibo,
Description:	1 electronic resource (105 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 86-04, Section: B.
Notes:	Advisors: Tan, Sheldon Committee members: Kim, Hyoseung; Tseng, Hung-Wei.
Contained By:	Dissertations Abstracts International86-04B.
Subject:	Engineering.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31301688
ISBN:	9798896073512

VLSI Design for Reliable and Stochastic Computing /
Liu, Yibo,

VLSI Design for Reliable and Stochastic Computing /Yibo Liu. - 1 electronic resource (105 pages)

Source: Dissertations Abstracts International, Volume: 86-04, Section: B.

The reliability of Very Large Scale Integration (VLSI) circuits is crucial in modern electronic devices. VLSI circuits, which contain millions of transistors, are vulnerable to a variety of reliability issues such as electromigration (EM), time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and hot carrier injection (HCI). These issues can lead to circuit failure and reduce the lifetime of electronic devices. This dissertation merged several works to present a study to mitigate the aging effects for VLSI circuits from multiple aspects. Firstly, due to the unidirectional current of the on-chip power grid, its aging effect is dominated by EM, this paper proposed a on-chip power grid EM-aware IR drop prediction method accelerated by machine learning (ML)techniques, and a matching fast EM-aware IR drop fixing method for on-chip power grid. Traditionally, VLSI reliability analysis and prediction have been performed using physics-based models and simulators. These models, however, are computationally intensive and can be time-consuming to run. This thesis paper presented a framework that machine learning techniques is adopted to model full-chip EM-aware IR drop, and a derived fast power grid sizing strategy, which leads to significant speedup over the existing analytical method. Secondly, with the continuous scaling of transistor sizes, the two dominant aging effects on arithmetic circuit and transistors are NBTI and HCI. The NBTI and HCI effects have various impacts such threshold voltage drift for the MOS transistors, device lifetime reduction, and circuit speed slowing down. Hence, this paper adopts stochastic computing techniques to enable an efficient trade-off among accuracy, latency, power, and area for error-tolerant applications.

English

ISBN: 9798896073512Subjects--Topical Terms:

210888
Engineering.
Subjects--Index Terms:

Electromigration

VLSI Design for Reliable and Stochastic Computing /
LDR:03260nmm a22004333i 4500 001 676330
005 20250420214343.5
006 m o d
007 cr|nu||||||||
008 250901s2024 miu||||||m |||||||eng d
020 $a 9798896073512
035 $a (MiAaPQD)AAI31301688
035 $a AAI31301688
040 $a MiAaPQD $b eng $c MiAaPQD $e rda
100 1 $a Liu, Yibo, $e author. $3 990107
245 1 0 $a VLSI Design for Reliable and Stochastic Computing / $c Yibo Liu.
264 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2024
300 $a 1 electronic resource (105 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertations Abstracts International, Volume: 86-04, Section: B.
500 $a Advisors: Tan, Sheldon Committee members: Kim, Hyoseung; Tseng, Hung-Wei.
502 $b Ph.D. $c University of California, Riverside $d 2024.
520 $a The reliability of Very Large Scale Integration (VLSI) circuits is crucial in modern electronic devices. VLSI circuits, which contain millions of transistors, are vulnerable to a variety of reliability issues such as electromigration (EM), time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and hot carrier injection (HCI). These issues can lead to circuit failure and reduce the lifetime of electronic devices. This dissertation merged several works to present a study to mitigate the aging effects for VLSI circuits from multiple aspects. Firstly, due to the unidirectional current of the on-chip power grid, its aging effect is dominated by EM, this paper proposed a on-chip power grid EM-aware IR drop prediction method accelerated by machine learning (ML)techniques, and a matching fast EM-aware IR drop fixing method for on-chip power grid. Traditionally, VLSI reliability analysis and prediction have been performed using physics-based models and simulators. These models, however, are computationally intensive and can be time-consuming to run. This thesis paper presented a framework that machine learning techniques is adopted to model full-chip EM-aware IR drop, and a derived fast power grid sizing strategy, which leads to significant speedup over the existing analytical method. Secondly, with the continuous scaling of transistor sizes, the two dominant aging effects on arithmetic circuit and transistors are NBTI and HCI. The NBTI and HCI effects have various impacts such threshold voltage drift for the MOS transistors, device lifetime reduction, and circuit speed slowing down. Hence, this paper adopts stochastic computing techniques to enable an efficient trade-off among accuracy, latency, power, and area for error-tolerant applications.
546 $a English
590 $a School code: 0032
650 4 $a Engineering. $3 210888
650 4 $a Electrical engineering. $3 454503
650 4 $a Computer engineering. $3 212944
653 $a Electromigration
653 $a Machine learning
653 $a Stochastic computing
653 $a VLSI reliability
653 $a Very Large Scale Integration circuits
690 $a 0537
690 $a 0544
690 $a 0464
710 2 $a University of California, Riverside. $b Electrical Engineering. $3 660199
720 1 $a Tan, Sheldon $e degree supervisor.
773 0 $t Dissertations Abstracts International $g 86-04B.
790 $a 0032
791 $a Ph.D.
792 $a 2024
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31301688