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Circuit-technology co-optimization of SRAM design in advanced CMOS nodes

Record Type:	Electronic resources : Monograph/item
Title/Author:	Circuit-technology co-optimization of SRAM design in advanced CMOS nodesby Hsiao-Hsuan Liu, Francky Catthoor.
Author:	Liu, Hsiao-Hsuan.
other author:	Catthoor, Francky.
Published:	Cham :Springer Nature Switzerland :2025.
Description:	xviii, 288 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Static random access memory.
Online resource:	https://doi.org/10.1007/978-3-031-76109-6
ISBN:	9783031761096$q(electronic bk.)

Circuit-technology co-optimization of SRAM design in advanced CMOS nodes
Liu, Hsiao-Hsuan.

Circuit-technology co-optimization of SRAM design in advanced CMOS nodes[electronic resource] /by Hsiao-Hsuan Liu, Francky Catthoor. - Cham :Springer Nature Switzerland :2025. - xviii, 288 p. :ill., digital ;24 cm.

Introduction -- SRAM Basic Principles and Simulation Methodologies -- SRAM Bitcell Scaling Roadmap Towards CFETs -- SRAM Subarray- and Macro-level DTCO PPA Analysis -- Beyond Traditional SRAM Bitcell-Level Scaling -- Future Design Direction for SRAM Data Array Towards A14 -- Summaries.

Modern computing engines-CPUs, GPUs, and NPUs-require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes. The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss. In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes. Identifies and develops PPA booster within SRAM design for deeply scaled nodes. Leverages bitcell scaling to drive PPA improvements alongside technology advancements. Explores alternative subarray design to enhance PPA in interconnect-centric technology nodes.

ISBN: 9783031761096$q(electronic bk.)

Standard No.: 10.1007/978-3-031-76109-6doiSubjects--Topical Terms:

992262
Static random access memory.

LC Class. No.: TK7895.M4

Dewey Class. No.: 621.39732

Circuit-technology co-optimization of SRAM design in advanced CMOS nodes
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505 0 $a Introduction -- SRAM Basic Principles and Simulation Methodologies -- SRAM Bitcell Scaling Roadmap Towards CFETs -- SRAM Subarray- and Macro-level DTCO PPA Analysis -- Beyond Traditional SRAM Bitcell-Level Scaling -- Future Design Direction for SRAM Data Array Towards A14 -- Summaries.
520 $a Modern computing engines-CPUs, GPUs, and NPUs-require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes. The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss. In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes. Identifies and develops PPA booster within SRAM design for deeply scaled nodes. Leverages bitcell scaling to drive PPA improvements alongside technology advancements. Explores alternative subarray design to enhance PPA in interconnect-centric technology nodes.
650 0 $a Static random access memory. $3 992262
650 0 $a Metal oxide semiconductors, Complementary. $3 184467
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