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Design and architecture for signal and image processing18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025 : proceedings /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design and architecture for signal and image processingedited by Jordane Lorandel, Ahmed Kamaleldin.
Reminder of title:	18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025 : proceedings /
remainder title:	DASIP 2025
other author:	Lorandel, Jordane.
corporate name:
Published:	Cham :Springer Nature Switzerland :2025.
Description:	xvi, 133 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Signal processingTextbooks.
Online resource:	https://doi.org/10.1007/978-3-031-87897-8
ISBN:	9783031878978$q(electronic bk.)

Design and architecture for signal and image processing18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025 : proceedings /
Design and architecture for signal and image processing18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025 : proceedings /[electronic resource] :DASIP 2025edited by Jordane Lorandel, Ahmed Kamaleldin. - Cham :Springer Nature Switzerland :2025. - xvi, 133 p. :ill. (some col.), digital ;24 cm. - Lecture notes in computer science,155691611-3349 ;. - Lecture notes in computer science ;4891..

Specialized Hardware Architecture for Efficient Processing. -- CSD-Driven Speedup in RISC-V Processor. -- Efficient FPGA implementation of ViT Non-Linear Functions. -- LiFT: Lightweight,FPGA-tailored 3D object detection based on LIDAR data. -- Efficient Processing using AI for Image, Vision and Signal Applications. -- A practical HW-Aware NAS flow for AI vision applications on embedded heterogeneous SoCs. -- Endoscopy image classification for wireless cpasules with CNNs on microcontroller-based platforms. -- Joint Underwater Depth Estimation and Dehazing from Single Image using Attention U-Net. -- KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition. -- Analysis of Emerging Techniques for Signal Processing Applications. -- Novel scheduling and shifter networks for 5G LDPC decoders. -- Comparison Between In-core Hardware IDS, Off-core Hardware IDS and Software IDS. -- Comparative Study of Memory Optimization Techniques for Dataflow-modeled Applications.

This book constitutes the refereed conference proceedings of the 18th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2025, held in Barcelona, Spain, during January 20-22, 2025. The 10 full papers included in this book were carefully reviewed and selected from 23 submissions.They were organized in topical sections as follows: Specialized Hardware Architecture for Efficient Processing; Efficient Processing using AI for Image, Vision and Signal Applications, and Analysis of Emerging Techniques for Signal Processing Applications.

ISBN: 9783031878978$q(electronic bk.)

Standard No.: 10.1007/978-3-031-87897-8doiSubjects--Topical Terms:

450732
Signal processing
--Textbooks.

LC Class. No.: TK5102.9 / .C66 2025

Dewey Class. No.: 621.3822

Design and architecture for signal and image processing18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025 : proceedings /
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520 $a This book constitutes the refereed conference proceedings of the 18th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2025, held in Barcelona, Spain, during January 20-22, 2025. The 10 full papers included in this book were carefully reviewed and selected from 23 submissions.They were organized in topical sections as follows: Specialized Hardware Architecture for Efficient Processing; Efficient Processing using AI for Image, Vision and Signal Applications, and Analysis of Emerging Techniques for Signal Processing Applications.
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