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LLVM compiler for RISC-V architectur...

Bataev, Alexey.

LLVM compiler for RISC-V architecturea unique approach to vectorization /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	LLVM compiler for RISC-V architectureby Alexey Bataev.
其他題名:	a unique approach to vectorization /
作者:	Bataev, Alexey.
出版者:	Berkeley, CA :Apress :2025.
面頁冊數:	xiv, 322 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Reduced instruction set computers.
電子資源:	https://doi.org/10.1007/979-8-8688-2169-1
ISBN:	9798868821691$q(electronic bk.)

LLVM compiler for RISC-V architecturea unique approach to vectorization /
Bataev, Alexey.

LLVM compiler for RISC-V architecturea unique approach to vectorization /[electronic resource] :by Alexey Bataev. - Berkeley, CA :Apress :2025. - xiv, 322 p. :ill., digital ;24 cm. - Maker innovations series,2948-2550. - Maker innovations series..

Chapter 1: Introduction -- RISC-V Vector Extension Introduction -- Chapter 2: RISC-V RVV support in clang-based compiler -- Chapter 3: Vector support extensions in clang-based compilers -- Chapter 4: RISC-V RVV specific LLVM-based optimizations -- Chapter 5: LLVM Loop Vectorizer -- Chapter 6: LLVM SLP Vectorizer.

ISBN: 9798868821691$q(electronic bk.)

Standard No.: 10.1007/979-8-8688-2169-1doiSubjects--Topical Terms:

467609
Reduced instruction set computers.

LC Class. No.: QA76.5

Dewey Class. No.: 004.16

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