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Microchip fabrication /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Microchip fabrication /Peter Van Zant.
remainder title:	A practical guide to semiconductor processing
Author:	Van Zant, Peter,
Description:	xxiii, 548 pages :illustrations ;25 cm
Subject:	SemiconductorsDesign and construction.
ISBN:	9780071821018

Microchip fabrication /
Van Zant, Peter,

Microchip fabrication / : Subtitle on cover:A practical guide to semiconductor processingPeter Van Zant. - Sixth edition. - xxiii, 548 pages :illustrations ;25 cm

Includes bibliographical references and index.

Ch. 1: The Semiconductor Industry: Birth of an Industry -- The Solid-State Era -- Integrated Circuits (ICs) -- Process and Product Trends -- Moore's Law -- Decreasing Feature Size -- Increasing Chip and Wafer Size -- Reduction in Defect Density -- Increase in Interconnection Levels -- The Semiconductor Industry Association Roadmap -- Chip Cost -- Industry Organization -- Stages of Manufacturing -- Six Decades of Advances in Microchip Fabrication Processes -- The Nano Era -- Ch. 2: Properties of Semiconductor Materials and Chemicals: Atomic Structure -- The Bohr Atom -- The Periodic Table of the Elements -- Electrical Conduction -- Conductors -- Dielectrics and Capacitors -- Resistors -- Intrinsic Semiconductors -- Doped Semiconductors -- Electron and Hole Conduction -- Carrier Mobility -- Semiconductor Production Materials -- Germanium and Silicon -- Semiconducting Compounds -- Silicon Germanium -- Engineered Substrates -- Ferroelectric Materials -- Diamond Semiconductors -- Process Chemicals -- Molecules, Compounds, and Mixtures -- Ions -- States of Matter -- Solids, Liquids, and Gases -- Plasma State -- Properties of Matter -- Temperature -- Density, Specific Gravity, and Vapor Density -- Pressure and Vacuum -- Acids, Alkalis, and Solvents -- Acids and Alkalis -- Solvents -- Chemical Purity and Cleanliness -- Safety Issues -- The Material Safety Data Sheet -- Ch. 3: Crystal Growth and Silicon Wafer Preparation: Semiconductor Silicon Preparation -- Silicon Wafer Preparation Stages -- Crystalline Materials -- Unit Cells -- Poly and Single Crystals -- Crystal Orientation -- Crystal Growth -- Czochralski Method -- Liquid-Encapsulated Czochralski -- Float Zone -- Crystal and Wafer Quality -- Point Defects -- Dislocations -- Growth Defects -- Wafer Preparation -- End Cropping -- Diameter Grinding -- Crystal Orientation, Conductivity, and Resistivity Check -- Grinding Orientation Indicators -- Wafer Slicing -- Wafer Marking -- Rough Polish -- Chemical Mechanical Polishing -- Backside Processing -- Double-Sided Polishing -- Edge Grinding and Polishing -- Wafer Evaluation -- Oxidation -- Packaging -- Wafer Types and Uses -- Reclaim Wafers -- Engineered Wafers (Substrates).

"This fully updated introduction to semiconductor manufacturing--the industry that drives high tech--offers a low-math, straightforward approach to the entire process, from raw materials through shipping the finished, packaged device"--

ISBN: 9780071821018

LCCN: 2013043733

Nat. Bib. Agency Control No.: 016546865UkSubjects--Topical Terms:

182501
Semiconductors
--Design and construction.

LC Class. No.: TK7871.85 / .V36 2014

Microchip fabrication /
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019 $a 1302905242
020 $a 9780071821018 $q (hardback)
020 $a 0071821015 $q (hardback)
035 $a (OCoLC)875891718 $z (OCoLC)1302905242
035 $a ocn875891718
040 $a DLC $b eng $e rda $c STF $d OCLCF $d OCLCQ $d OCLCO $d OCLCL $d OCLCQ $d OCLCL $d HQU $d OCLCQ
042 $a pcc
049 $a NUKM
050 0 0 $a TK7871.85 $b .V36 2014
100 1 $a Van Zant, Peter, $e author. $3 1010717
245 1 0 $a Microchip fabrication / $c Peter Van Zant.
246 1 $i Subtitle on cover: $a A practical guide to semiconductor processing
250 $a Sixth edition.
264 1 $a New York : $b McGraw-Hill Education, $c [2014]
264 4 $c ©2014
300 $a xxiii, 548 pages : $b illustrations ; $c 25 cm
336 $a text $b txt $2 rdacontent
337 $a unmediated $b n $2 rdamedia
338 $a volume $b nc $2 rdacarrier
340 $p illustration $0 http://rdaregistry.info/termList/IllusContent/1014 $2 rdaill
504 $a Includes bibliographical references and index.
505 0 $a Ch. 1: The Semiconductor Industry: Birth of an Industry -- The Solid-State Era -- Integrated Circuits (ICs) -- Process and Product Trends -- Moore's Law -- Decreasing Feature Size -- Increasing Chip and Wafer Size -- Reduction in Defect Density -- Increase in Interconnection Levels -- The Semiconductor Industry Association Roadmap -- Chip Cost -- Industry Organization -- Stages of Manufacturing -- Six Decades of Advances in Microchip Fabrication Processes -- The Nano Era -- Ch. 2: Properties of Semiconductor Materials and Chemicals: Atomic Structure -- The Bohr Atom -- The Periodic Table of the Elements -- Electrical Conduction -- Conductors -- Dielectrics and Capacitors -- Resistors -- Intrinsic Semiconductors -- Doped Semiconductors -- Electron and Hole Conduction -- Carrier Mobility -- Semiconductor Production Materials -- Germanium and Silicon -- Semiconducting Compounds -- Silicon Germanium -- Engineered Substrates -- Ferroelectric Materials -- Diamond Semiconductors -- Process Chemicals -- Molecules, Compounds, and Mixtures -- Ions -- States of Matter -- Solids, Liquids, and Gases -- Plasma State -- Properties of Matter -- Temperature -- Density, Specific Gravity, and Vapor Density -- Pressure and Vacuum -- Acids, Alkalis, and Solvents -- Acids and Alkalis -- Solvents -- Chemical Purity and Cleanliness -- Safety Issues -- The Material Safety Data Sheet -- Ch. 3: Crystal Growth and Silicon Wafer Preparation: Semiconductor Silicon Preparation -- Silicon Wafer Preparation Stages -- Crystalline Materials -- Unit Cells -- Poly and Single Crystals -- Crystal Orientation -- Crystal Growth -- Czochralski Method -- Liquid-Encapsulated Czochralski -- Float Zone -- Crystal and Wafer Quality -- Point Defects -- Dislocations -- Growth Defects -- Wafer Preparation -- End Cropping -- Diameter Grinding -- Crystal Orientation, Conductivity, and Resistivity Check -- Grinding Orientation Indicators -- Wafer Slicing -- Wafer Marking -- Rough Polish -- Chemical Mechanical Polishing -- Backside Processing -- Double-Sided Polishing -- Edge Grinding and Polishing -- Wafer Evaluation -- Oxidation -- Packaging -- Wafer Types and Uses -- Reclaim Wafers -- Engineered Wafers (Substrates).
505 0 $a Ch. 4: Overview of Wafer Fabrication and Packaging: Goal of Wafer Fabrication -- Wafer Terminology -- Chip Terminology -- Basic Wafer-Fabrication Operations -- Layering -- Patterning -- Circuit Design -- Reticle and Masks -- Doping -- Heat Treatments -- Example Fabrication Process -- Wafer Sort -- Packaging -- Ch. 5: Contamination Control: The Problem -- Contamination-Caused Problems -- Contamination Sources -- General Sources -- Air -- Clean Air Strategies -- Cleanroom Workstation Strategy -- Tunnel or Bay Concept -- Micro- and Mini-Environments -- Temperature, Humidity, and Smog -- Cleanroom Construction -- Construction Materials -- Cleanroom Elements -- Personnel-Generated Contamination -- Process Water -- Process Chemicals -- Equipment -- Cleanroom Materials and Supplies -- Cleanroom Maintenance -- Wafer-Surface Cleaning -- Particulate Removal -- Wafer Scrubbers -- High-Pressure Water Cleaning -- Organic Residues -- Inorganic Residues -- Chemical-Cleaning Solutions -- General Chemical Cleaning -- Oxide Layer Removal -- Room Temperature and Ozonated Chemistries -- Water Rinsing -- Drying Techniques -- Contamination Detection -- Ch. 6: Productivity and Process Yields: Yield Measurement Points -- Accumulative Wafer-Fabrication Yield -- Wafer-Fabrication Yield Limiters -- Number of Process Steps -- Wafer Breakage and Warping -- Process Variation -- Mask Defects -- Wafer-Sort Yield Factors -- Wafer Diameter and Edge Die -- Wafer Diameter and Die Size -- Wafer Diameter and Crystal Defects -- Wafer Diameter and Process Variations -- Die Area and Defect Density -- Circuit Density and Defect Density -- Number of Process Steps -- Feature Size and Defect Size -- Process Cycle Time -- Wafer-Sort Yield Formulas -- Assembly and Final Test Yields -- Overall Process Yields -- Ch. 7: Oxidation: Silicon Dioxide Layer Uses -- Surface Passivation -- Doping Barrier -- Surface Dielectric -- Device Dielectric (MOS Gates) -- Device Oxide Thicknesses -- Thermal Oxidation Mechanisms -- Influences on the Oxidation Rate -- Thermal Oxidation Methods -- Horizontal Tube Furnaces -- Temperature Control System -- Source Cabinet -- Vertical Tube Furnaces -- Rapid Thermal Processing -- High-Pressure Oxidation -- Oxidant Sources -- Oxidation Processes -- Preoxidation Wafer Cleaning -- Postoxidation Evaluation -- Surface Inspection -- Oxide Thickness -- Oxide and Furnace Cleanliness -- Thermal Nitridation.
505 0 $a Ch. 10: Next Generation Lithography: Challenges of Next Generation Lithography -- High-Pressure Mercury Lamp Sources -- Excimer Lasers -- Extreme Ultraviolet -- X-Rays -- Electron Beam or Direct Writing -- Numerical Aperture of a Lens -- Other Exposure Issues -- Variable Numerical Aperture Lenses -- Immersion Exposure System -- Amplified Resist -- Contrast Effects -- Other Resolution Challenges and Solutions -- Off-Axis Illumination -- Lens Issues and Reflection Systems -- Phase-Shift Masks -- Optical Proximity Corrected or Optical Process Correction -- Annular-Ring Illumination -- Pellicles -- Surface Problems -- Resist Light Scattering -- Subsurface Reflectivity -- Antireflective Coatings -- Standing Waves -- Planarization -- Photoresist Process Advances -- Multilayer Resist or Surface Imaging -- Silylation or DESIRE Process -- Polyimide Planarization Layers -- Etchback Planarization -- Dual-Damascene Process -- Chemical Mechanical Polishing -- Slurry -- Polishing Rates -- Planarity -- Post-CMP Clean -- CMP Tools -- CMP Summary -- Reflow -- Image Reversal -- Contrast Enhancement Layers -- Dyed Resists -- Improving Etch Definition -- Lift-Off Process -- Self-Aligned Structures -- Etch Profile Control -- Ch. 11: Doping: The Diffusion Concept -- Formation of a Doped Region and Junction -- The N-P Junction -- Doping Process Goals -- Graphical Representation of Junctions -- Concentration versus Depth Graphs -- Lateral Diffusion -- Same-Type Doping -- Diffusion Process Steps -- Deposition -- Lateral Diffusion -- Same-Type Doping -- Dopant Sources -- Drive-In Oxidation -- Oxidation Effects -- to Ion Implantation -- Concept of Ion Implantation -- Ion-Implantation System -- Implant Species Sources -- Ionization Chamber -- Mass Analyzing or Ion Selection -- Acceleration Tube -- Wafer Charging -- Beam Focus -- Neutral Beam Trap -- Beam Scanning -- End Station and Target Chamber -- Ion-Implant Masks -- Dopant Concentration in Implanted Regions -- Crystal Damage -- Annealing and Dopant Activation -- Channeling -- Evaluation of Implanted Layers -- Uses of Ion Implantation -- The Future of Doping.
505 0 $a Ch. 15: The Business of Wafer Fabrication: Moore's Law and the New Wafer-Fabrication Business -- Wafer-Fabrication Costs -- Overhead -- Materials -- Equipment -- Labor -- Production Cost Factors -- Yield -- Yield Improvements -- Yield and Productivity -- Book-to-Bill Ratio -- Cost of Ownership -- Automation -- Process Automation -- Wafer-Loading Automation -- Clustering -- Wafer-Delivery Automation -- Closed-Loop Control-System Automation -- Factory-Level Automation -- Equipment Standards -- Fab Floor Layout -- Batch versus Single-Wafer Processing -- Green Fabs -- Statistical Process Control -- Inventory Control -- Just-in-Time Inventory Control -- Quality Control and Certification -- ISO 9000 -- Line Organization -- Ch. 16: to Devices and Integrated Circuit Formation: Semiconductor-Device Formation -- Resistors -- Capacitors -- Diodes -- Transistors -- Field-Effect Transistors -- Alternatives to MOSFET Scaling Challenges -- Conductors -- Integrated-Circuit Formation -- Bipolar Circuit Formation -- MOS Integrated Circuit Formation -- Bi-MOS -- Silicon on Insulator Isolation -- Superconductors -- Microelectromechanical Systems -- Strain Gauges -- Batteries -- Light-Emitting Diodes -- Optoelectronics -- Solar Cells -- Temperature Sensing -- Acoustic Wave Devices -- Ch. 17: to Integrated Circuits: Circuit Basics -- Integrated Circuit Types -- Logic Circuits -- Memory Circuits -- Redundancy -- The Next Generation -- Ch. 18: Packaging: Chip Characteristics -- Package Functions and Design -- Substantial Lead System -- Physical Protection -- Environmental Protection -- Heat Dissipation -- Common Package Parts -- Cleanliness and Static Control -- Basic Bonding Processes -- Wire Bonding Process -- Prebonding Wafer Preparation -- Die Separation -- Die Pick and Place -- Die Inspection -- Die Attach -- Wire Bonding -- Tape Automated Bonding Process -- Bump or Ball Flip-Chip Bonding -- Example Bump or Ball Process -- Copper Metallization (Damascene) Bump Bonding -- Reflow -- Die Separation and Die Pick and Place -- Alignment of Die to Package -- Attachment to Package (or Substrate) -- Deflux -- Underfillment -- Encapsulation -- Postbonding and Preseal Inspection -- Sealing Techniques -- Lead Plating -- Plating Process Flows -- Lead Trimming -- Deflashing -- Package Marking -- Final Testing -- Environmental Tests -- Electrical Testing -- Burn-In Tests -- Package Design -- Metal Cans -- Pin Grid Arrays -- Ball-Grid Arrays or Flip-Chip Ball-Grid Arrays -- Quad Packages -- Thin Packages -- Chip-Scale Packages -- Lead on Chip -- Three-Dimensional Packages -- Stacking Die Techniques -- Three-Dimensional Enabling Technologies -- Hybrid Circuits -- Multichip Modules -- The Known Good Die Problem -- Package Type or Technology Summary -- Package or PCB Connections -- Bare Die Techniques and Blob Top.
520 $a "This fully updated introduction to semiconductor manufacturing--the industry that drives high tech--offers a low-math, straightforward approach to the entire process, from raw materials through shipping the finished, packaged device"-- $c Provided by publisher.
650 0 $a Semiconductors $x Design and construction. $3 182501
650 0 $a Integrated circuits $x Design and construction. $3 184690
650 6 $a Circuits intégrés $x Conception et construction. $3 1010921
994 $a C0 $b TWNUK