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Low thermal budget processing for se...

Rajendran, Bipin.

Low thermal budget processing for sequential three dimensional integrated circuit fabrication.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Low thermal budget processing for sequential three dimensional integrated circuit fabrication.
作者:	Rajendran, Bipin.
面頁冊數:	95 p.
附註:	Adviser: R. Fabian W. Pease.
附註:	Source: Dissertation Abstracts International, Volume: 67-09, Section: B, page: 5296.
Contained By:	Dissertation Abstracts International67-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3235327
ISBN:	9780542895425

Low thermal budget processing for sequential three dimensional integrated circuit fabrication.
Rajendran, Bipin.

Low thermal budget processing for sequential three dimensional integrated circuit fabrication. - 95 p.

Adviser: R. Fabian W. Pease.

Thesis (Ph.D.)--Stanford University, 2006.

Low temperature deposition techniques are promising candidates for forming the gate dielectric layer of upper level transistors. In our process, low-pressure chemical vapor deposition (LPCVD) is used to form the SiO2 gate insulator at 450°C. Implanted dopants at the source/drain and the amorphous silicon gate are activated using 30 ns pulses from a KrF excimer laser (248 nm wavelength) delivering more than 10 MW/cm2. Both n and p channel transistors exhibit on-off ratios in excess of 106, with drive currents and sub-threshold slopes similar to that of conventionally fabricated transistors. This process technology could be used to fabricate multiple levels of active devices in 3D ICs in a sequential manner.

ISBN: 9780542895425Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Low thermal budget processing for sequential three dimensional integrated circuit fabrication.
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245 1 0 $a Low thermal budget processing for sequential three dimensional integrated circuit fabrication.
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500 $a Source: Dissertation Abstracts International, Volume: 67-09, Section: B, page: 5296.
502 $a Thesis (Ph.D.)--Stanford University, 2006.
520 # $a Low temperature deposition techniques are promising candidates for forming the gate dielectric layer of upper level transistors. In our process, low-pressure chemical vapor deposition (LPCVD) is used to form the SiO2 gate insulator at 450°C. Implanted dopants at the source/drain and the amorphous silicon gate are activated using 30 ns pulses from a KrF excimer laser (248 nm wavelength) delivering more than 10 MW/cm2. Both n and p channel transistors exhibit on-off ratios in excess of 106, with drive currents and sub-threshold slopes similar to that of conventionally fabricated transistors. This process technology could be used to fabricate multiple levels of active devices in 3D ICs in a sequential manner.
520 # $a Recently, there has been great interest in developing three-dimensional (3D) integrated circuits (ICs) with multiple layers of transistors stacked one above the other. In this scheme, the active devices on different planes are separated by insulating layers (not more than a few microns thick) and are connected to each other by metal wires running vertically. Thus, it would be possible to increase the number of transistors per unit area and improve the overall circuit performance by reducing the average interconnect length. If the transistors at different levels are made sequentially on crystalline layers above existing circuitry, three-dimensional circuits with more than a million vertical wires per square millimeter could be fabricated. However, conventional high temperature processes such as dopant activation and gate oxidation would adversely affect the circuits at lower levels. Therefore, these steps have to be changed.
520 # $a The new process sequence features pulsed laser annealing for dopant activation. The thermal transient behavior during laser annealing is studied by solving the light absorption and thermal diffusion equations. Calculations and experiments indicate that it is possible to use laser annealing to activate dopants at the upper levels of 3D ICs while maintaining the quality and reliability of circuits at lower levels.
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