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Low-noise low-power design for phase...

Dai, Fa Foster.

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Low-noise low-power design for phase-locked loopsby Feng Zhao, Fa Foster Dai.
Reminder of title:	multi-phase high-performance oscillators /
Author:	Zhao, Feng.
other author:	Dai, Fa Foster.
Published:	Cham :Springer International Publishing :2015.
Description:	xiii, 96 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Phase-locked loops.
Online resource:	http://dx.doi.org/10.1007/978-3-319-12200-7
ISBN:	9783319122007 (electronic bk.)

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /
Zhao, Feng.

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /[electronic resource] :by Feng Zhao, Fa Foster Dai. - Cham :Springer International Publishing :2015. - xiii, 96 p. :ill. (some col.), digital ;24 cm.

Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13um SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions.

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

ISBN: 9783319122007 (electronic bk.)

Standard No.: 10.1007/978-3-319-12200-7doiSubjects--Topical Terms:

182354
Phase-locked loops.

LC Class. No.: TK7872.P38

Dewey Class. No.: 621.3815364

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /
LDR:01975nmm a2200313 a 4500 001 460578
003 DE-He213
005 20150714150532.0
006 m d
007 cr nn 008maaau
008 151110s2015 gw s 0 eng d
020 $a 9783319122007 (electronic bk.)
020 $a 9783319121994 (paper)
024 7 $a 10.1007/978-3-319-12200-7 $2 doi
035 $a 978-3-319-12200-7
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7872.P38
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815364 $2 23
090 $a TK7872.P38 $b Z63 2015
100 1 $a Zhao, Feng. $3 712099
245 1 0 $a Low-noise low-power design for phase-locked loops $h [electronic resource] : $b multi-phase high-performance oscillators / $c by Feng Zhao, Fa Foster Dai.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2015.
300 $a xiii, 96 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13um SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions.
520 $a This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
650 0 $a Phase-locked loops. $3 182354
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
650 2 4 $a Signal, Image and Speech Processing. $3 273768
700 1 $a Dai, Fa Foster. $3 712100
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-12200-7
950 $a Engineering (Springer-11647)