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[ subject:"Systems on a chip" ]
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System-on-chip test architectures :n...
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Stroud, Charles E.
System-on-chip test architectures :nanometer design for testability /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
System-on-chip test architectures :edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
其他題名:
nanometer design for testability /
其他作者:
Wang, Laung-Terng.
出版者:
Amsterdam ;Morgan Kaufmann Publishers,c2008.
面頁冊數:
xxxvi, 856 p. :ill. ;25 cm.
叢書名:
The Morgan Kaufmann series in systems on silicon
標題:
Integrated circuitsVery large scale integration
ISBN:
9780123739735
System-on-chip test architectures :nanometer design for testability /
System-on-chip test architectures :
nanometer design for testability /edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. - Amsterdam ;Morgan Kaufmann Publishers,c2008. - xxxvi, 856 p. :ill. ;25 cm. - The Morgan Kaufmann series in systems on silicon .
Includes bibliographical references and index.
ISBN: 9780123739735
LCCN: 2007023373 Subjects--Topical Terms:
257763
Integrated circuits
--Very large scale integration
LC Class. No.: TK7895.E42 / S978 2008
Dewey Class. No.: 621.39/5
System-on-chip test architectures :nanometer design for testability /
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