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三維電腦繪圖系統晶片之測試介面控制電路與可測試性設計技術 = The T...

吳俊毅

三維電腦繪圖系統晶片之測試介面控制電路與可測試性設計技術 = The Test Interface Controller and DFT Technique for 3D Graphics SoC

Record Type:	Language materials, printed : monographic
Paralel Title:	The Test Interface Controller and DFT Technique for 3D Graphics SoC
Author:	吳俊毅,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	2009[民98]
Description:	11, 91面圖，表 : 30公分;
Subject:	可測試性的3D電腦繪圖晶片
Subject:	3D Chip on Embedded System
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/85130988125340484141
Summary:	近幾年來，由於嵌入式系統的興起與可攜式應用層面的的擴大，應用在手機、PAD等等的可攜式系統的層面與需求逐年增加，而為了讓一般使用者能有方便簡易操作環境，因而使用圖形化使用者介面(Graphical User Interface)以利使用者方便操作。且由於積體電路的運算速度也逐年加速，所以各廠商利用這個機會將圖形化使用者介面(Graphical User Interface)再度強化，使得可攜式產品與一般使用者產生強大的互動，也因為為了與使用者能有更強大的互動圖形化使用者介面(Graphical User Interface)，因此在可攜式產品中，其繪圖晶片佔有相當大的地位，所有圖形化使用者介面(Graphical User Interface)的互動運算皆需要透過繪圖晶片的運算，才能夠把畫面顯示在螢幕上，可見繪圖晶片的發展重要性。由於晶片的設計漸漸朝向System-on-Chip(SoC)的方向發展，也因為如此，為了讓晶片能夠更有效率的工作，因此出現了將矽智產(Intellectual Properties)模組化的概念，而相對的為了使矽智產(Intellectual Properties)能夠快速的被使用，因此在System-on-Chip(SoC)的設計上必須利用匯流排的架構來協助System-on-Chip(SoC)設計能夠快速的將矽智產(Intellectual Properties)銜接使用。目前System-on-Chip(SoC)的匯流排多數是採用AMBA (Advanced Microcontroller Bus Architecture)系統匯流排，透過匯流排的整合快速的將矽智產掛載在System-on-Chip(SoC)上，但也因為System-on-Chip(SoC)設計上其利用矽智產(Intellectual Properties)數量逐年增加，導致System-on-Chip(SoC)晶片內部的電路複雜度大大提升，相對的系統測試難度也就大為提升。本篇論文在系統測試上，利用了IEEE-1500與Test Interface Controller(TIC)來進行系統測試，透過兩種不同的測試機制，已達到系統晶片測試最佳化、測試時間最佳化與測試電路面積最佳化。 In recent years, due to the rise of embedded systems and the expansion of portable products application, the level and demand of application used in portal system such as cell phones, PAD, and so on has increased year by year. In order to allow users to have a easy simple operating environment, the use of Graphical User Interface(GUI)can let users operate products easier. Moreover, as the integrated circuit and the computing speed is also speeding up year by year, so the manufacturers take advantage of this opportunity to strengthen the GUI interface once again. It makes portable products having strong interaction with end-users. For taking a more powerful GUI interaction interface to end-users, the “Graphics Chips” play a important role in a portable product. All the GUI interaction interface needs to operate by graphics chips to display images on the screen. Thus, the importance of the development about graphic chips can bee seen here.As the design of chips gradually towards to the development of System on Chip (SoC) development. In order to allow the chip can work more efficiently, the concept of Intellectual Properties (IP) modular was emerged. To enhance the usage of IP fast, the design of SoC must take the architecture of BUS to help SoC design can quickly use with IP. At present, the most SoC BUS designed by AMBA system, through the rapid integration of BUS, the IP can be mounted into SoC design. However, because the quantities of SoC design using IP increased year by year, it results the inside SoC circuit gets difficulty and complicity, in

三維電腦繪圖系統晶片之測試介面控制電路與可測試性設計技術 = The Test Interface Controller and DFT Technique for 3D Graphics SoC
吳, 俊毅

三維電腦繪圖系統晶片之測試介面控制電路與可測試性設計技術 = The Test Interface Controller and DFT Technique for 3D Graphics SoC / 吳俊毅撰 - [高雄市] : 撰者, 2009[民98]. - 11, 91面 ; 圖，表 ; 30公分.
參考書目：面88-91.
可測試性的3D電腦繪圖晶片3D Chip on Embedded System

三維電腦繪圖系統晶片之測試介面控制電路與可測試性設計技術 = The Test Interface Controller and DFT Technique for 3D Graphics SoC
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330 $a 近幾年來，由於嵌入式系統的興起與可攜式應用層面的的擴大，應用在手機、PAD等等的可攜式系統的層面與需求逐年增加，而為了讓一般使用者能有方便簡易操作環境，因而使用圖形化使用者介面(Graphical User Interface)以利使用者方便操作。且由於積體電路的運算速度也逐年加速，所以各廠商利用這個機會將圖形化使用者介面(Graphical User Interface)再度強化，使得可攜式產品與一般使用者產生強大的互動，也因為為了與使用者能有更強大的互動圖形化使用者介面(Graphical User Interface)，因此在可攜式產品中，其繪圖晶片佔有相當大的地位，所有圖形化使用者介面(Graphical User Interface)的互動運算皆需要透過繪圖晶片的運算，才能夠把畫面顯示在螢幕上，可見繪圖晶片的發展重要性。由於晶片的設計漸漸朝向System-on-Chip(SoC)的方向發展，也因為如此，為了讓晶片能夠更有效率的工作，因此出現了將矽智產(Intellectual Properties)模組化的概念，而相對的為了使矽智產(Intellectual Properties)能夠快速的被使用，因此在System-on-Chip(SoC)的設計上必須利用匯流排的架構來協助System-on-Chip(SoC)設計能夠快速的將矽智產(Intellectual Properties)銜接使用。目前System-on-Chip(SoC)的匯流排多數是採用AMBA (Advanced Microcontroller Bus Architecture)系統匯流排，透過匯流排的整合快速的將矽智產掛載在System-on-Chip(SoC)上，但也因為System-on-Chip(SoC)設計上其利用矽智產(Intellectual Properties)數量逐年增加，導致System-on-Chip(SoC)晶片內部的電路複雜度大大提升，相對的系統測試難度也就大為提升。本篇論文在系統測試上，利用了IEEE-1500與Test Interface Controller(TIC)來進行系統測試，透過兩種不同的測試機制，已達到系統晶片測試最佳化、測試時間最佳化與測試電路面積最佳化。 In recent years, due to the rise of embedded systems and the expansion of portable products application, the level and demand of application used in portal system such as cell phones, PAD, and so on has increased year by year. In order to allow users to have a easy simple operating environment, the use of Graphical User Interface(GUI)can let users operate products easier. Moreover, as the integrated circuit and the computing speed is also speeding up year by year, so the manufacturers take advantage of this opportunity to strengthen the GUI interface once again. It makes portable products having strong interaction with end-users. For taking a more powerful GUI interaction interface to end-users, the “Graphics Chips” play a important role in a portable product. All the GUI interaction interface needs to operate by graphics chips to display images on the screen. Thus, the importance of the development about graphic chips can bee seen here.As the design of chips gradually towards to the development of System on Chip (SoC) development. In order to allow the chip can work more efficiently, the concept of Intellectual Properties (IP) modular was emerged. To enhance the usage of IP fast, the design of SoC must take the architecture of BUS to help SoC design can quickly use with IP. At present, the most SoC BUS designed by AMBA system, through the rapid integration of BUS, the IP can be mounted into SoC design. However, because the quantities of SoC design using IP increased year by year, it results the inside SoC circuit gets difficulty and complicity, in
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