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Low-power heterogeneous reconfigurab...

University of California, Berkeley.

Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network.
Author:	Zhang, Hui.
Description:	113 p.
Notes:	Chair: Jan M. Rabaey.
Notes:	Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4758.
Contained By:	Dissertation Abstracts International65-09B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3147057
ISBN:	0496055852

Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network.
Zhang, Hui.

Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network. - 113 p.

Chair: Jan M. Rabaey.

Thesis (Ph.D.)--University of California, Berkeley, 2004.

A heterogeneous reconfigurable digital signal processor consists of an array of coarse-grained computing units and memory units connected by reconfigurable local and global communications structures. The processor also contains distributed control units that dynamically analyze data operations and perform reconfiguration accordingly. The computing units can be independently configured to perform a variety of basic computational functions.

ISBN: 0496055852Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network.
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245 1 0 $a Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network.
300 $a 113 p.
500 $a Chair: Jan M. Rabaey.
500 $a Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4758.
502 $a Thesis (Ph.D.)--University of California, Berkeley, 2004.
520 # $a A heterogeneous reconfigurable digital signal processor consists of an array of coarse-grained computing units and memory units connected by reconfigurable local and global communications structures. The processor also contains distributed control units that dynamically analyze data operations and perform reconfiguration accordingly. The computing units can be independently configured to perform a variety of basic computational functions.
520 # $a Future portable devices with rich multimedia functions ask for increasingly powerful digital signal processors that deliver high performance, ultra low power, low cost, and good flexibility. Flexibility is a necessity to achieve high system integration (to save the space and cost) in the presence of multiple standards, and to support the diverse and rapidly evolving multimedia applications. While ASICs or dedicated hardware can achieve the lowest power consumption and the highest performance for a specific application, they can't meet the flexibility requirement. At another end, general-purpose instruction-based microprocessors or DSPs either fall short of performance or are too power inefficient. Recently, reconflgurable architectures, which are characterized as both software programmable and post-fabrication hardware configurable, have emerged as key alternative solutions providing the performance, energy-efficiency and cost similar to ASIC while being flexible enough for the target wireless and embedded multimedia application domains.
520 # $a This work thoroughly analyzes the algorithms of wireless speech coding and embedded multimedia processing such as video processing, and to identify the underlying computational kernels that account for a large fraction of execution time and energy. The main challenge of designing a reconfigurable processor is how to map these computational kernels effectively to the configurable computing units and to design a reconfigurable interconnect network that effectively combines these kernels into operational system. This thesis work describes the design methodology of an energy-efficient interconnect network, from both circuits and architecture perspective. Several novel low-swing interconnect schemes and hierarchical interconnect network architectures are proposed to achieve high energy efficiency. To verify the effectiveness of the proposed heterogeneous reconfigurable architecture, prototype chips were designed for wireless speech coding and embedded multimedia processing respectively. Measured results and benchmark studies demonstrate the effectiveness of the heterogenous reconfigurable architecture.
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