國立高雄大學圖資館 |

語系: 繁體中文

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Verification by error modeling :usin...

Radecka, Katarzyna.

Verification by error modeling :using testing techniques in hardware verification

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Verification by error modeling :written by Katarzyna Radecka, Zeljko Zilic.
其他題名:	using testing techniques in hardware verification
作者:	Radecka, Katarzyna.
其他作者:	Zilic, Zeljko.
出版者:	Boston :Springer Science + Business Media, Inc.,c2004.
面頁冊數:	xiv, 216 p. :ill., digital ;25 cm.
叢書名:	Frontiers in electronic testing ;
Contained By:	Springer e-books
標題:	Integrated circuitsVery large scale integration
電子資源:	http://libsw.nuk.edu.tw:81/login?url=http://dx.doi.org/10.1007/b105974
ISBN:	9780306487392 (electronic bk.)

Verification by error modeling :using testing techniques in hardware verification
Radecka, Katarzyna.

Verification by error modeling :using testing techniques in hardware verification[electronic resource] /written by Katarzyna Radecka, Zeljko Zilic. - Boston :Springer Science + Business Media, Inc.,c2004. - xiv, 216 p. :ill., digital ;25 cm. - Frontiers in electronic testing ;25.

ISBN: 9780306487392 (electronic bk.)Subjects--Topical Terms:

184578
Integrated circuits
--Very large scale integration

LC Class. No.: TK7874.75 / .R33 2004

Dewey Class. No.: 621.395

Verification by error modeling :using testing techniques in hardware verification
LDR:00868nmm 2200241 a 4500 001 217661
003 GreenPo
005 20081020161902.0
006 m d
007 cr nn 008maaau
008 091014s2004 mau j eng d
020 $a 9780306487392 (electronic bk.)
020 $a 9781402076527 (paper)
035 $a 978-1-4020-7652-7
050 0 0 $a TK7874.75 $b .R33 2004
082 0 0 $a 621.395 $2 22
090 $a TK7874.75 $b .R126 2004
100 1 $a Radecka, Katarzyna. $3 347413
245 1 0 $a Verification by error modeling : $b using testing techniques in hardware verification $h [electronic resource] / $c written by Katarzyna Radecka, Zeljko Zilic.
260 # $a Boston : $c c2004. $b Springer Science + Business Media, Inc.,
300 $a xiv, 216 p. : $b ill., digital ; $c 25 cm.
440 0 $a Frontiers in electronic testing ; $v 25
650 # 0 $a Integrated circuits $x Very large scale integration $x Computer-aided design. $3 184578
650 # 0 $a Integrated circuits $x Verification. $3 185514
650 # 0 $a Error analysis (Mathematics) $3 182680
700 1 # $a Zilic, Zeljko. $3 347412
710 2 # $a SpringerLink (Online service) $3 273601
773 0 # $t Springer e-books
856 4 0 $u http://libsw.nuk.edu.tw:81/login?url=http://dx.doi.org/10.1007/b105974
950 $a Engineering