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Hardware architectures for post-quan...
~
Soni, Deepraj.
Hardware architectures for post-quantum digital signature schemes
Record Type:
Electronic resources : Monograph/item
Title/Author:
Hardware architectures for post-quantum digital signature schemesby Deepraj Soni ... [et al.].
other author:
Soni, Deepraj.
Published:
Cham :Springer International Publishing :2021.
Description:
xxii, 170 p. :ill., digital ;24 cm.
Contained By:
Springer Nature eBook
Subject:
Cryptography.
Online resource:
https://doi.org/10.1007/978-3-030-57682-0
ISBN:
9783030576820$q(electronic bk.)
Hardware architectures for post-quantum digital signature schemes
Hardware architectures for post-quantum digital signature schemes
[electronic resource] /by Deepraj Soni ... [et al.]. - Cham :Springer International Publishing :2021. - xxii, 170 p. :ill., digital ;24 cm.
Introduction -- qTESLA -- CRYSTALS -Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
ISBN: 9783030576820$q(electronic bk.)
Standard No.: 10.1007/978-3-030-57682-0doiSubjects--Topical Terms:
189522
Cryptography.
LC Class. No.: TK5102.94
Dewey Class. No.: 005.824
Hardware architectures for post-quantum digital signature schemes
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This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
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based on 0 review(s)
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EB TK5102.94 .H267 2021 2021
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https://doi.org/10.1007/978-3-030-57682-0
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