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High energy efficiency neural network processor with combined digital and computing-in-memory architecture

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	High energy efficiency neural network processor with combined digital and computing-in-memory architectureby Jinshan Yue.
作者:	Yue, Jinshan.
出版者:	Singapore :Springer Nature Singapore :2024.
面頁冊數:	xvi, 118 p. :ill. (chiefly col.), digital ;24 cm.
附註:	"Doctoral thesis accepted by Tsinghua University, Beijing, China."
Contained By:	Springer Nature eBook
標題:	Neural networks (Computer science)
電子資源:	https://doi.org/10.1007/978-981-97-3477-1
ISBN:	9789819734771$q(electronic bk.)

High energy efficiency neural network processor with combined digital and computing-in-memory architecture
Yue, Jinshan.

High energy efficiency neural network processor with combined digital and computing-in-memory architecture[electronic resource] /by Jinshan Yue. - Singapore :Springer Nature Singapore :2024. - xvi, 118 p. :ill. (chiefly col.), digital ;24 cm. - Springer theses,2190-5061. - Springer theses..

"Doctoral thesis accepted by Tsinghua University, Beijing, China."

Introduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.

Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI) The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.

ISBN: 9789819734771$q(electronic bk.)

Standard No.: 10.1007/978-981-97-3477-1doiSubjects--Topical Terms:

181982
Neural networks (Computer science)

LC Class. No.: QA76.87

Dewey Class. No.: 006.32

High energy efficiency neural network processor with combined digital and computing-in-memory architecture
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