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A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop /

Record Type:	Electronic resources : Monograph/item
Title/Author:	A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop /Jaewon Sohn.
Author:	Sohn, Jaewon,
Description:	1 electronic resource (61 pages)
Notes:	Source: Masters Abstracts International, Volume: 85-11.
Notes:	Advisors: Koo, Jabeom Committee members: Shoop, Barry L.; Koo, Jabeom.
Contained By:	Masters Abstracts International85-11.
Subject:	Electrical engineering.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31295379
ISBN:	9798382591216

A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop /
Sohn, Jaewon,

A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop /Jaewon Sohn. - 1 electronic resource (61 pages)

Source: Masters Abstracts International, Volume: 85-11.

This study focuses on designing a low-noise, high-speed integrator charge pump for Phase-Locked Loop (PLL) for 7G WiFi. To provide a steady and noiseless frequency as a reference clock for other units, PLLs require a ripple-free control volt- age for their internal oscillator. The conventional charge pump circuit, which relies on cascoded CMOS switches for generating the control voltage, introduces numerous non-ideal characteristics that result in undesired fluctuations in the voltage. Common issues with this topology, including current mismatch, RC filter noise, and charge sharing, are addressed and resolved by completely eliminating the conventional switch-mode charge pump and replacing it with an active non-inverting differential integrator for the equivalent integration operation. Designed and simulated with TSMC 65nm technology, the integrator charge pump circuit successfully operates in the 7G WiFi frequency band, and even at higher frequencies with a power consumption of 1.6mW. Although the power consumption may increase due to the inclusion of active components, the proposed design substantiates its ability to remove undesired voltage variation, operate at high frequencies, and reduce the complexity of the design by eliminating the inversion delay previously needed for driving the CMOS switches.

English

ISBN: 9798382591216Subjects--Topical Terms:

454503
Electrical engineering.
Subjects--Index Terms:

Charge pump

A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop /
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245 1 2 $a A High-Speed Integrator Design for the Charge Pump of a 7G WiFi Phase-Locked Loop / $c Jaewon Sohn.
264 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2024
300 $a 1 electronic resource (61 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 85-11.
500 $a Advisors: Koo, Jabeom Committee members: Shoop, Barry L.; Koo, Jabeom.
502 $b M.E. $c The Cooper Union for the Advancement of Science and Art $d 2024.
520 $a This study focuses on designing a low-noise, high-speed integrator charge pump for Phase-Locked Loop (PLL) for 7G WiFi. To provide a steady and noiseless frequency as a reference clock for other units, PLLs require a ripple-free control volt- age for their internal oscillator. The conventional charge pump circuit, which relies on cascoded CMOS switches for generating the control voltage, introduces numerous non-ideal characteristics that result in undesired fluctuations in the voltage. Common issues with this topology, including current mismatch, RC filter noise, and charge sharing, are addressed and resolved by completely eliminating the conventional switch-mode charge pump and replacing it with an active non-inverting differential integrator for the equivalent integration operation. Designed and simulated with TSMC 65nm technology, the integrator charge pump circuit successfully operates in the 7G WiFi frequency band, and even at higher frequencies with a power consumption of 1.6mW. Although the power consumption may increase due to the inclusion of active components, the proposed design substantiates its ability to remove undesired voltage variation, operate at high frequencies, and reduce the complexity of the design by eliminating the inversion delay previously needed for driving the CMOS switches.
546 $a English
590 $a School code: 0057
650 4 $a Electrical engineering. $3 454503
650 4 $a Communication. $3 180335
653 $a Charge pump
653 $a Phase-Locked Loop
653 $a WiFi frequency band
653 $a Switch-mode charge pump
690 $a 0544
690 $a 0459
710 2 $a The Cooper Union for the Advancement of Science and Art. $b Electrical Engineering. $3 886588
720 1 $a Koo, Jabeom $e degree supervisor.
773 0 $t Masters Abstracts International $g 85-11.
790 $a 0057
791 $a M.E.
792 $a 2024
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31295379