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Hardware-Accelerated Human Pose Estimation: Exploring the Potential of Versal Field-Programmable Gate-Arrays /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Hardware-Accelerated Human Pose Estimation: Exploring the Potential of Versal Field-Programmable Gate-Arrays /Vibishan Wigneswaran.
作者:	Wigneswaran, Vibishan,
面頁冊數:	1 electronic resource (59 pages)
附註:	Source: Masters Abstracts International, Volume: 87-06.
附註:	Advisors: Leeser, Miriam Committee members: Schirner, Gunar; Xu, Xiaolin.
Contained By:	Masters Abstracts International87-06.
標題:	Electrical engineering.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=32400884
ISBN:	9798270246129

Hardware-Accelerated Human Pose Estimation: Exploring the Potential of Versal Field-Programmable Gate-Arrays /
Wigneswaran, Vibishan,

Hardware-Accelerated Human Pose Estimation: Exploring the Potential of Versal Field-Programmable Gate-Arrays /Vibishan Wigneswaran. - 1 electronic resource (59 pages)

Source: Masters Abstracts International, Volume: 87-06.

The rapid growth of artificial intelligence (AI) has driven significant advancements in convolutional neural networks (CNNs), recurrent neural networks (RNNs), and transformer-based architectures. While software frameworks continue to evolve, the bottleneck for achieving high-throughput, low-latency machine learning inference lies in hardware. Industry efforts have largely focused on optimizing graphics processing unit (GPU) architectures for both training and inference, leaving field-programmable gate arrays (FPGAs) comparatively underexplored. This presents an opportunity: modern FPGA platforms may offer substantial performance and efficiency benefits for real-time machine learning workloads.This thesis investigates the potential of AMD's Versal Adaptive system-on-chip (SoC), particularly its AI Engine (AIE) tile architecture, in accelerating inference for human pose estimation. Contrary to traditional FPGA workflows that rely solely on programmable logic, the Versal platform integrates dedicated single instruction, multiple data (SIMD) vector processors, high-bandwidth memory access, and a configurable network-on-chip (NoC), enabling highly parallel inference pipelines. Although training remains dominated by GPU platforms, inference on FPGA architectures offers advantages in flexibility, customization, and tighter control over latency and data movement for specific workloads.To evaluate the practicality of FPGA-based acceleration in a real-world context, this work targets BlazePose, a widely used open-source human pose estimation model. BlazePose represents a meaningful case study due to its computational complexity, real-time requirements, and accessibility to hobbyists and researchers. By mapping the BlazePose inference heads onto the Versal AI Engine, this research evaluates hardware suitability at the kernel and subsystem level. The implementation demonstrates that the BlazePose inference heads can be realized on a small number of AI Engine tiles while preserving numerical equivalence in fixed-point validation. Further, AI Engine software simulation and compute-bound analysis indicate the potential for substantially lower kernel execution time than a CPU-only TensorFlow Lite (TFLite) baseline; however, end-to-end on-board latency measurements depend on resolving platform integration constraints. Demonstrating such capability may lower the barrier to hardware acceleration and encourage broader adoption among engineers and developers seeking domain-specific, high-performance embedded AI solutions, particularly in environments where Versal-class accelerators are already deployed.

English

ISBN: 9798270246129Subjects--Topical Terms:

454503
Electrical engineering.
Subjects--Index Terms:

Blazepose

Hardware-Accelerated Human Pose Estimation: Exploring the Potential of Versal Field-Programmable Gate-Arrays /
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520 $a The rapid growth of artificial intelligence (AI) has driven significant advancements in convolutional neural networks (CNNs), recurrent neural networks (RNNs), and transformer-based architectures. While software frameworks continue to evolve, the bottleneck for achieving high-throughput, low-latency machine learning inference lies in hardware. Industry efforts have largely focused on optimizing graphics processing unit (GPU) architectures for both training and inference, leaving field-programmable gate arrays (FPGAs) comparatively underexplored. This presents an opportunity: modern FPGA platforms may offer substantial performance and efficiency benefits for real-time machine learning workloads.This thesis investigates the potential of AMD's Versal Adaptive system-on-chip (SoC), particularly its AI Engine (AIE) tile architecture, in accelerating inference for human pose estimation. Contrary to traditional FPGA workflows that rely solely on programmable logic, the Versal platform integrates dedicated single instruction, multiple data (SIMD) vector processors, high-bandwidth memory access, and a configurable network-on-chip (NoC), enabling highly parallel inference pipelines. Although training remains dominated by GPU platforms, inference on FPGA architectures offers advantages in flexibility, customization, and tighter control over latency and data movement for specific workloads.To evaluate the practicality of FPGA-based acceleration in a real-world context, this work targets BlazePose, a widely used open-source human pose estimation model. BlazePose represents a meaningful case study due to its computational complexity, real-time requirements, and accessibility to hobbyists and researchers. By mapping the BlazePose inference heads onto the Versal AI Engine, this research evaluates hardware suitability at the kernel and subsystem level. The implementation demonstrates that the BlazePose inference heads can be realized on a small number of AI Engine tiles while preserving numerical equivalence in fixed-point validation. Further, AI Engine software simulation and compute-bound analysis indicate the potential for substantially lower kernel execution time than a CPU-only TensorFlow Lite (TFLite) baseline; however, end-to-end on-board latency measurements depend on resolving platform integration constraints. Demonstrating such capability may lower the barrier to hardware acceleration and encourage broader adoption among engineers and developers seeking domain-specific, high-performance embedded AI solutions, particularly in environments where Versal-class accelerators are already deployed.
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