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Digital logic design sing Verilogcod...

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Digital logic design sing Verilogcoding and RTL synthesis /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Digital logic design sing Verilogby Vaibbhav Taraate.
Reminder of title:	coding and RTL synthesis /
Author:	Taraate, Vaibbhav.
Published:	New Delhi :Springer India :2016.
Description:	xxiii, 416 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Logic designData processing.
Online resource:	http://dx.doi.org/10.1007/978-81-322-2791-5
ISBN:	9788132227915$q(electronic bk.)

Digital logic design sing Verilogcoding and RTL synthesis /
Taraate, Vaibbhav.

Digital logic design sing Verilogcoding and RTL synthesis /[electronic resource] :by Vaibbhav Taraate. - New Delhi :Springer India :2016. - xxiii, 416 p. :ill. (some col.), digital ;24 cm.

Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.

ISBN: 9788132227915$q(electronic bk.)

Standard No.: 10.1007/978-81-322-2791-5doiSubjects--Topical Terms:

182348
Logic design
--Data processing.

LC Class. No.: TK7868.L6

Dewey Class. No.: 621.395

Digital logic design sing Verilogcoding and RTL synthesis /
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505 0 $a Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
520 $a This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.
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