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Advanced HDL synthesis and SOC proto...

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Advanced HDL synthesis and SOC prototypingRTL design using verilog /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Advanced HDL synthesis and SOC prototypingby Vaibbhav Taraate.
其他題名:	RTL design using verilog /
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer Singapore :2019.
面頁冊數:	xxi, 307 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Systems on a chip.
電子資源:	https://doi.org/10.1007/978-981-10-8776-9
ISBN:	9789811087769$q(electronic bk.)

Advanced HDL synthesis and SOC prototypingRTL design using verilog /
Taraate, Vaibbhav.

Advanced HDL synthesis and SOC prototypingRTL design using verilog /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2019. - xxi, 307 p. :ill., digital ;24 cm.

Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

ISBN: 9789811087769$q(electronic bk.)

Standard No.: 10.1007/978-981-10-8776-9doiSubjects--Topical Terms:

224012
Systems on a chip.

LC Class. No.: TK7895.E42 / T373 2019

Dewey Class. No.: 621.3815

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505 0 $a Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520 $a This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
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