國立高雄大學圖資館 |

Language: English

Back

SystemVerilog for hardware descripti...

SpringerLink (Online service)

SystemVerilog for hardware descriptionRTL design and verification /

Record Type:	Electronic resources : Monograph/item
Title/Author:	SystemVerilog for hardware descriptionby Vaibbhav Taraate.
Reminder of title:	RTL design and verification /
Author:	Taraate, Vaibbhav.
Published:	Singapore :Springer Singapore :2020.
Description:	xxi, 252 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	SystemVerilog (Computer hardware description language)
Online resource:	https://doi.org/10.1007/978-981-15-4405-7
ISBN:	9789811544057$q(electronic bk.)

SystemVerilog for hardware descriptionRTL design and verification /
Taraate, Vaibbhav.

SystemVerilog for hardware descriptionRTL design and verification /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2020. - xxi, 252 p. :ill., digital ;24 cm.

Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

ISBN: 9789811544057$q(electronic bk.)

Standard No.: 10.1007/978-981-15-4405-7doiSubjects--Topical Terms:

670683
SystemVerilog (Computer hardware description language)

LC Class. No.: TK7885.7 / .T373 2020

Dewey Class. No.: 621.392

SystemVerilog for hardware descriptionRTL design and verification /
LDR:02332nmm a2200325 a 4500 001 580499
003 DE-He213
005 20201028092313.0
006 m
007 cr
008 210105s2020
020 $a 9789811544057$q(electronic bk.)
020 $a 9789811544040$q(paper)
024 7 $a 10.1007/978-981-15-4405-7 $2 doi
035 $a 978-981-15-4405-7
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7885.7 $b .T373 2020
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.392 $2 23
090 $a TK7885.7 $b .T176 2020
100 1 $a Taraate, Vaibbhav. $3 747702
245 1 0 $a SystemVerilog for hardware description $h [electronic resource] : $b RTL design and verification / $c by Vaibbhav Taraate.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2020.
300 $a xxi, 252 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.
520 $a This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
650 0 $a SystemVerilog (Computer hardware description language) $3 670683
650 1 4 $a Circuits and Systems. $3 274416
650 2 4 $a Control Structures and Microprogramming. $3 274663
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
650 2 4 $a Electronic Circuits and Devices. $3 495609
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-981-15-4405-7
950 $a Engineering (Springer-11647)