國立高雄大學圖資館 |

Language: English

Back

ASIC design and synthesis : RTL desi...

Taraate, Vaibbhav.

ASIC design and synthesis : RTL design using Verilog /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	ASIC design and synthesis : Vaibbhav Taraate
Reminder of title:	RTL design using Verilog /
Author:	Taraate, Vaibbhav.
Published:	[S.l.] :SPRINGER,2021.
Description:	XXI, 330 pages. : ilustr. ; 25 cm.
Subject:	Electronic circuits.
ISBN:	9813346418

ASIC design and synthesis : RTL design using Verilog /
Taraate, Vaibbhav.

ASIC design and synthesis : RTL design using Verilog / Vaibbhav Taraate - [S.l.] :SPRINGER,2021. - XXI, 330 pages. : ilustr. ; 25 cm.

Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

ISBN: 9813346418Subjects--Topical Terms:

182223
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

ASIC design and synthesis : RTL design using Verilog /
LDR:02195nam a2200253 a 4500 001 591913
003 OCoLC
005 20210720031958.0
008 210720s2021 xx 0|| 0 eng d
020 $a 9813346418
020 $a 9789813346413
021 0 2 $a nam a2200229 a 4500
035 $a (OCoLC)1202752318
035 $a on1202752318
040 $a YDX $b eng $c YDX $d DKU $d OCLCO $d OCLCF
049 $a NUKM
050 # 4 $a TK7888.4
082 0 4 $a 621.3815 $2 23
100 1 $a Taraate, Vaibbhav. $3 747702
245 1 0 $a ASIC design and synthesis : $b RTL design using Verilog / $c Vaibbhav Taraate
260 # $a [S.l.] : $b SPRINGER, $c 2021.
300 $a XXI, 330 pages. : $b ilustr. ; $c 25 cm.
505 0 # $a Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520 # $a This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
650 # 0 $a Electronic circuits. $3 182223
650 # 0 $a Microprogramming. $3 310294
650 # 0 $a Logic design. $3 182234
938 $a YBP Library Services $b YANK $n 17082872
994 $a C0 $b TWNUK