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Digital logic design using Verilogcoding and RTL synthesis /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Digital logic design using Verilogby Vaibbhav Taraate.
Reminder of title:	coding and RTL synthesis /
Author:	Taraate, Vaibbhav.
Published:	Singapore :Springer Singapore :2022.
Description:	xxv, 604 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
Subject:	Logic designData processing.
Online resource:	https://doi.org/10.1007/978-981-16-3199-3
ISBN:	9789811631993$q(electronic bk.)

Digital logic design using Verilogcoding and RTL synthesis /
Taraate, Vaibbhav.

Digital logic design using Verilogcoding and RTL synthesis /[electronic resource] :by Vaibbhav Taraate. - Second edition. - Singapore :Springer Singapore :2022. - xxv, 604 p. :ill., digital ;24 cm.

Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

ISBN: 9789811631993$q(electronic bk.)

Standard No.: 10.1007/978-981-16-3199-3doiSubjects--Topical Terms:

182348
Logic design
--Data processing.

LC Class. No.: TK7868.L6 / T37 2022

Dewey Class. No.: 621.395

Digital logic design using Verilogcoding and RTL synthesis /
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300 $a xxv, 604 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
520 $a This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
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