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四閘極金氧半場效電晶體之具氧化層基體絕緣結構(含/不含)氧化層介面缺陷電...

國立高雄大學電機工程學系碩士班

四閘極金氧半場效電晶體之具氧化層基體絕緣結構(含/不含)氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the SOI Quadruple-Gate MOSFETs with/without the Localized Interface Trapped Charges

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	The Investigation on Subthreshold Behavior Model for the SOI Quadruple-Gate MOSFETs with/without the Localized Interface Trapped Charges
作者:	高鴻文,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2014[民103]
面頁冊數:	194面部份彩圖，表 : 30公分;
標題:	四閘極金氧半場效電晶體
標題:	Quadruple-Gate MOSFETs
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/25710870973127550496
附註:	參考書目：面175-178
附註:	103年12月16日公開
附註:	內容為英文
摘要註:	過去數十年來，有許多關於平面單閘極電晶體與雙閘極電晶體之熱載子效應引起的次臨界行為研究，熱載子效應所引起的氧化層缺陷介面電荷，造成臨界電壓漂移及元件的電子參數特性的改變。截至目前為止，含氧化層缺陷介面電荷之四閘極電晶體的次臨界電特性的研究仍相當欠缺，而針對植入帶電電荷改變電特性之記憶體元件(Charge Trapped or Injection Memory Device)應用而言，實有必要研究其次臨界行為特性與表面缺陷電荷之關係，以期該元件將來被有效應用於記憶體電路中，本論文乃基於帕森方程式三維近似解與全三維解，成功地推導出含氧化層缺陷介面電荷之四閘極電晶體具氧化層基體絕緣結構之次臨界行為解析模型。本論文乃基於帕森方程式、微縮理論及周長加權近似法，成功地推導出四閘極電晶體具氧化層基體絕緣結構之次臨界行為解析模型，此模型不僅準確顯示出電位分佈(potential distribution)、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應，而且此模型與元件模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路設計之模擬。 Several studies have modeled the hot-carrier-induced threshold voltage of the planar and the double-gate MOSFETs in the past decade. The hot-carrier-induced positive or negative charges can be trapped in the interface between the gate oxide and the silicon film, which can further cause the shift of the threshold voltage and deteriorate the electrical characteristic parameters of the device. Until now, there is no literature to investigate the subthreshold behavior model of the Quadruple-Gate (QG) MOSFETs with the localized interface trapped charges. With the application for Charge Trapped or Injection Memory Device, we report the Quasi 3-D/Fully 3-D analytical model of the subthreshold behavior for the Quadruple-gate MOSFETs. In this thesis, based on the exact solution of the Poisson equation,scaling theory and perimeter- weighted-sum approach, an analytical subthreshold model for the Quadruple-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model explicitly shows the potential distribution, subthreshold slope, subthreshold current, threshold voltage, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the device simulator ”DESSIS”,and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced QG MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the SOI QG transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.

四閘極金氧半場效電晶體之具氧化層基體絕緣結構(含/不含)氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the SOI Quadruple-Gate MOSFETs with/without the Localized Interface Trapped Charges
高, 鴻文

四閘極金氧半場效電晶體之具氧化層基體絕緣結構(含/不含)氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the SOI Quadruple-Gate MOSFETs with/without the Localized Interface Trapped Charges / 高鴻文撰 - [高雄市] : 撰者, 2014[民103]. - 194面 ; 部份彩圖，表 ; 30公分.
參考書目：面175-178103年12月16日公開內容為英文.
四閘極金氧半場效電晶體Quadruple-Gate MOSFETs

四閘極金氧半場效電晶體之具氧化層基體絕緣結構(含/不含)氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the SOI Quadruple-Gate MOSFETs with/without the Localized Interface Trapped Charges
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330 $a 過去數十年來，有許多關於平面單閘極電晶體與雙閘極電晶體之熱載子效應引起的次臨界行為研究，熱載子效應所引起的氧化層缺陷介面電荷，造成臨界電壓漂移及元件的電子參數特性的改變。截至目前為止，含氧化層缺陷介面電荷之四閘極電晶體的次臨界電特性的研究仍相當欠缺，而針對植入帶電電荷改變電特性之記憶體元件(Charge Trapped or Injection Memory Device)應用而言，實有必要研究其次臨界行為特性與表面缺陷電荷之關係，以期該元件將來被有效應用於記憶體電路中，本論文乃基於帕森方程式三維近似解與全三維解，成功地推導出含氧化層缺陷介面電荷之四閘極電晶體具氧化層基體絕緣結構之次臨界行為解析模型。本論文乃基於帕森方程式、微縮理論及周長加權近似法，成功地推導出四閘極電晶體具氧化層基體絕緣結構之次臨界行為解析模型，此模型不僅準確顯示出電位分佈(potential distribution)、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應，而且此模型與元件模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路設計之模擬。 Several studies have modeled the hot-carrier-induced threshold voltage of the planar and the double-gate MOSFETs in the past decade. The hot-carrier-induced positive or negative charges can be trapped in the interface between the gate oxide and the silicon film, which can further cause the shift of the threshold voltage and deteriorate the electrical characteristic parameters of the device. Until now, there is no literature to investigate the subthreshold behavior model of the Quadruple-Gate (QG) MOSFETs with the localized interface trapped charges. With the application for Charge Trapped or Injection Memory Device, we report the Quasi 3-D/Fully 3-D analytical model of the subthreshold behavior for the Quadruple-gate MOSFETs. In this thesis, based on the exact solution of the Poisson equation,scaling theory and perimeter- weighted-sum approach, an analytical subthreshold model for the Quadruple-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model explicitly shows the potential distribution, subthreshold slope, subthreshold current, threshold voltage, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the device simulator ”DESSIS”,and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced QG MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the SOI QG transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.
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